Most modern PC systems are based an the PCI (Peripheral Component Interconnect) bus. However, the PCI bus has a lot of disadvantages because it was not originally created as a backplane bus, but as a way to connect integrated circuits. To avoid termination resistors PCI uses a very special modulation method known as Reflected Wave Switching, which utilizes the reflections from the far end of the transmission line to build up the signal level. The driver must have an output impedans, which corresponds to the impedance it looks into. When the driver is initiated, the signal level will initially be only 1/2 of the full level. However, because the bus is unterminated the reflections from the far end will be added to the signal, so that the level in this end attain the full level and with that exeeds the threshold level of the receiver. Then the reflected wave propagates towards the driver where it is absorbed in the resistor, so that the level on the entire bus has now attained full signal level and that there will be no more reflections.

The PCI bus has a lot of disadvantages, most of these coursed by the special modulation method.

• It requires a special driver or a serial resistor, so it is impossible to interface directly by means af e.g. standard High Speed CMOS logik.

• The ideal output impedance depends on the driver possition on the bus. If it is located in the middle, it will look into two transmission lines in parallel and should therefore have the half line impedance, that is, 25 ohm on a 50 ohm bus. On the other hand, if the driver is located in the far end, it will only look into one transmission line and should therefore have a 50 ohm impedance on a 50 ohm bus. The output impedance is therefore a compromise, which will never be ideal. The compromise is made even futher difficult because of the big resistor tollerances in an integrated circuit. Because of the compromise, the reflections will not be absorbed 100%, but continue backwards and forwards more times until a steady state has been obtained. This gives a strong limitation on the maximun bus speed.

• Because of the necessary reflection round-trips the bus must be really short to fulfill the demand for a 10 nS settle time. Originally, the PCI bus was only 4 inches long!

• The output impedance of the driver works as a low pass filter together with the input capacitance of the connected units. This reduces the maximum number of units to 8, but above 4 units it becomes very critical.

• The short bus length and the low number of units may make it necessary to split up the bus in more segments, which are connected by means of bridge units. This futher slows down the bus and makes it extremely complicated to interface to. A typical bus coupler is a circuit with over 200 legs and a specification of over 100 pages.

• It is not possible to reduce the bus speed as required, so that it may interface to slow cards.

• The PCI bus is unnecessary complex. One of the fundamental idears of the bus is that it should be able to work as a "traffic circle" with possibility for more traffic flows. However, in practice it is only data transfers between the CPU and any level 2 cache, which may benefit from this. The CPU depends 100% on access to the memory and the memory unit is also the only one, which the remaining units are interested in talking to directly (DMA). A separate bus between the CPU and the L2 cache could solve the problem in a far more simple and appropriate way.

For Innovatic, which has specialized itself in simple and reliable solutions, the PCI bus is of course much too complicated and critical. Therefore, we also have our own suggestion for an efficient and far more simple alternative.

A "modern" PC has a lot of different busses. There is a local bus to the memory, local busses to harddisk and diskette drive, a bus between the CPU and the graphical controller (AGP), one or more PCI busses and perhaps an ISA or EISA bus. Everything are connected by means of extremely complex bridge units and controllers. However, the Innovatic suggestion is one bus for the whole exept for a local bus between the CPU and any L2 cache. All other units - including CPU, memory, harddisk, diskette drive, CD-ROM etc. - are connected to a common backplane with a fast, passive bus. This makes the system much cheaper and easier to service, and there is no demand for any diskette or harddisk controllers.

By utilizing the same idears for bus arbitration and utilization of the reflections as in our fieldbus (see [Automation] [Fieldbus] ) it is possible to make a bus with the following properties:

• Extremely simple - demands almost as little logic as the ISA bus (Industry Standard Architecture - the old PC bus).

• Very simple modulation method - almost as simple as NRZ (Not Return to Zero). The reflections are utilized to improve the signal to noise level, but the bus do not depend on them. No bias distortion.

• No need for any termination resistors.

• Is able to use a standard High Speed CMOS driver and a standard High Speed CMOS schmitt-trigger receiver.

• Up to 32 connected units.

• Is able to adapt the speed to the actual requirement.

• Possibility for a faster speed than PCI. Theoretically op to 200 MHz is possible on a 15 inch bus based on a simple double sided epoxy printed circuit board.

• Multimasterbus with a very simple, but fast and efficient bus arbitration, which is also utilized as interrupt controller and DMA. It is therefore not necessary with a common bus arbitration unit, interrupt controller or DMA controller. All this are replaced by 3 groups of priority levels. The lowest group is used for e.g. memory access from the CPU, the next group for DMA transfers and the group with the higest priority for interrupts. If e.g. a harddisk wants to transfer some data by means of DMA, it do not need to use an external DMA controller. Because the bus is a multimaster bus it just performs a bus arbitration cycle when the bus becomes idle, which it always does at short intervals. If the harddisk has the highest priority between the units which are waiting for bus access, it will obtain the bus and may then itself transfer the data to the memory. In the same way, an arbitration cycle is performed if a unit request interrupt service. In this case, it will just be the CPU, which performs the data transfer. If more units request interrupt simultaneously it is of course the unit with the higest priority, which is serviced. After that a new arbitration cycle is performed.